Performance evaluation of inter-processor communication for an embedded heterogeneous multi-core processor
Shiao‐Li Tsao, Sung Yuan Lee · 2012
Embedded systems often use a heterogeneous multi-core processor to improve per-formance and energy efficiency. This multi-core processor is composed of a general pur-pose processor (GPP), which manages the program flow and I/O, and a digital signal pro-cessor (DSP), which processes mass data. An inter-processor communication (IPC) mech-anism is thus required to exchange data between a GPP and a DSP. This paper uses com-prehensive experiments to evaluate the IPC performance of an embedded heterogeneous multi-core processor under different design strategies. We further develop the IPC per-formance model and suggest dynamic adjustment of IPC strategies under environmental parameters and system resource constraints. Based on the results and findings, we im-prove the IPC performance of a voice over IP (VoIP) phone. Experimental results dem-onstrate that the GPP workload decreases significantly by 35 % without sacrificing the functionalities and voice quality of the VoIP system. Moreover, we apply the concept of dynamic adjustment of IPC strategies to an embedded media gateway. The simulation results demonstrate that the dynamic IPC strategy can considerably improve the system performance of the media gateway compared with the static IPC design approach.