An IEEE standard floating point chip
Ashish Komal, K. Goskel, P.W. Diodato, Jonathan Fields, U. V. Gumaste, Chaw Kung, Kingyao Lin, M. Lega, Peter Michael Maurer, Thomas Ng, Y.T. Oh, M. Thierbach · 1985
This paper will report on a 14MHz IEEE standard floating point coprocessor for a 32b microprocessor. Implemented in 1.75μ twin-tub CMOS, the chip supports single, double and extended double precision floating point, as well as 32b integer and 18 digit BCD operations.