A Coupled Multi-ALU Processing Node for a Highly Parallel Computer
Stephen W. Keckler · DSpace@MIT (Massachusetts Institute of Technology) · 1992
By 1995, improvements in semiconductor technology will allow as many as four highperformance floating-point ALUs and several megabits of memory to reside on a single chip. Multiple arithmetic units can be organized into a single processor to exploit instruction-level parallelism. Processor Coupling is a mechanism for controlling multiple ALUs to exploit both instructionlevel and inter-thread parallelism. Processor Coupling employs both compile time and runtime scheduling. The compiler statically schedules individual threads to discover available intra-thread instruction-level parallelism. The runtime scheduling mechanism interleaves threads, exploiting inter-thread parallelism to maintain high ALU utilization. ALUs are assigned to threads on a cycle by cycle basis, and several threads can be active concurrently. This thesis describes the architecture of a Processor Coupled node and evaluates parameters that affect performance. Processor Coupling is compared with a multiple ALU statical...