The design of the Caltech Mosaic C multicomputer
Charles L. Seitz, Nanette J. Boden, Jakov N. Seizovic, Wen-King Su · 1993
and Introduction The Caltech Mosaic C is an experimental, fine-grain multicomputer that employs single-chip nodes and advanced packaging technology to demonstrate the performance/cost advantages of the fine-grain-multicomputer architecture. Each Mosaic node includes 64KB of single-clock-cycle dynamic RAM; 2KB of self-test and bootstrap ROM; an 11MIPS processor; a packet interface; and a 60MB/s, two-dimensional, self-timed router. The node is a single, 9.25mm\\Theta10.00mm, 1.2¯m-feature-size, CMOS chip that, at V dd = 5V, operates at 30MHz and dissipates 0.5W. These chips are packaged by tapeautomated bonding (TAB) in 8\\Theta8 arrays on circuit boards that can, in turn, be composed in two dimensions to construct arbitrarily large arrays of nodes. In addition to the 8\\Theta8 boards, complete Mosaic systems require hostinterface boards that allow workstations to send and receive packets on Mosaic channels, and high-bandwidth cables. The Mosaic host-interface boards are built using memor...