FPGA based design of low power reconfigurable router for Network on Chip (NoC)
Amit Bhanwala, Mayank Kumar, Yogendera Kumar · 2015
FPGA based design of reconfigurable router for NoC applications is proposed in the present work. Design entry of the proposed router is done using Verilog Hardware Description Language (Verilog HDL). The router designed in the present work has four channels (namely, east, west, north and south) and a crossbar switch. Each channel consists of First in First out (FIFO) buffers and multiplexers. FIFO buffers are used to store the data and the input and output of the data are controlled using multiplexers. Firstly, south channel is designed which includes the design of FIFO and multiplexers. After that, the crossbar switch and other three channels are designed. All these designed channels, FIFO buffers, multiplexers and crossbar switches are integrated to form the complete router architecture. The proposed design is simulated using Modelsim and the RTL view is obtained using Xilinx ISE 13.4. Xilinx SPARTAN-6 FPGAs are used for synthesis of proposed design. Power dissipation of the proposed reconfigurable router is reduced using Power gating technique. Total power is calculated by the use of XPower Analyzer tool. Obtained results show that the proposed design consumes less power compared to the previously designed reconfigurable routers.