Linear bilateral CMOS resistor for neural-type circuits
Louiza Sellami, Sandeep Kumar Singh, R.W. Newcomb, Gyu Moon · 2005
A previous CMOS bilateral linear resistor is analyzed and shown to be reducible from four to two transistors with improved linearity. This is developed for neural-type circuits to allow its use in emulating both excitatory and inhibitory voltage variable synapses. Simulation results using parameters of MOSIS transistors are presented to verify the theory.