FPGA-memory tradeoff in the high-level synthesis of FPGA-based reconfigurable systems
Joko Istiyanto, S. Monaghan · 1994
The paper presents problems of applying synthesis techniques to FPGA-based design. The target architecture consists of a linear array of FPGAs in which to each FPGA there is a RAM attached to it. An attempt to utilise RAM is illustrated with random number generator as an example.>