A dual floating point coprocessor with an FMAC architecture
C. Heikes, Glenn Colon-Bonet · 2002
The CPU chip is implemented in a 5-layer metal 0.5 /spl mu/m CMOS process and delivers >360 SPECint92 and >550 SPECfp92. It is an out-of-order super-scalar processor with two integer, two floating point, two shift/merge and two load/store units. This paper describes circuits in the floating-point unit of this CPU.