Hardware Loop and Loop Skip Generation Algorithm for the Star Core® Architecture: Architecture, Application and Compiler Design Interaction in the Embedded Domain
Anca Burlacu-Zane · 2015
Lately it has been argued that standard architectures as modern x86 can outperform classic Digital Signal Processors in the embedded domain. X86 started to include some classical DSP features and have greater support for I/O, file access, extended memory etc. However, even those studies showed that it depends on the characteristics of the targeted domains. Specific algorithms (echo canceling etc) perform better on ASICs, memory intensive ones (audio/video players) are advantaged by GPUs, and coders/decoders perform best on Digital Signal Processors. Each architecture has its target applications and in order to succeed it needs associated tools. This paper starts by presenting a study on the compiler's view, how it is influenced by the targeted architecture and applications and how it can influence architecture design. It continues by introducing an algorithm for compiler automatic generation of hardware loop and associated loop skip for the Star Core® architecture, as a practical application.