Efficient implementation of rounding units
Neil Burgess, S.C. Knowles · 2003
This paper shows how IEEE 754 floating-point standard compliant rounding may be merged with carry-propagate addition in high-performance FPU designs. The paper considers addition/subtraction, multiplication and divide/square root operations and demonstrates that in every case one parallel prefix adder with a small amount of additional logic is sufficient to cover all rounding modes.