Implementation of Area Efficient Hybrid MBIST for Memory Clusters in Asynchronous SoC
Yasha Jyothi M Shirur, H. R. Lakshmi, Veena S. Chakravarthi · 2014
In current scenario, asynchronous MPSoC are of great demand owing to their power efficiency. As the design flow is getting redefined for the design of asynchronous MPSoC, test methodology needs review and redefinition. The heterogeneous memories operating at different frequencies are an integrated part of Asynchronous MPSoC. And BIST controllers with separate MBIST schemes are traditionally used to test each of these memories. This paper deals with an area efficient Hybrid MBIST controller implemented to test multiple memories in an Asynchronous SoC. The work has resulted in lesser area solution to the extent of 60% when compared with the conventional scheme. Also, the percentage of reduction increases if the number of memories increases in the design.