VHDLStyler - a script-based tool for IP design modification [SoC design]
T. Biichner, C. Smith · 2004
This paper describes a method to enable the transition from a given design environment to a modern SoC design flow at minimal cost, and with increased productivity for future designs. A Java-based tool is presented that allows the script-based modification of existing VHDL code for a wide range of applications.