Techniques for reducing hardware requirement of self checking combinational circuits
Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh · 2003
The authors present two methods that can be used to reduce the hardware requirement for a self checking implementation of a given combinational function. They give examples to show that these give very significant reduction over the traditional SFS implementation. They believe that by careful use of such optimizations, the size of self checking implementations can be brought down within acceptable limits for use in practice.>