Multiplier less FFR processor architecture for signal and image processing
R. Prasanthi, V. Anuradha, Subhendu Kumar Sahoo, Chandra Shekhar · 2005
A novel fixed-point 16-bit word-width 16-point FFT/IFFT processor architecture is proposed primarily for the application of signal and image processing. The 16-point FFT is realized by using Cooley-Tukey DIT (decimation in time) algorithm. This approach reduces the number of required complex multiplications compared to a normal DFT. Since multipliers are very power hungry elements in VLSI designs. they result in significant power consumption. So, the complex multiplication operations are realized using shift-and-add operations. The most important contribution to be noted here is that each and every multiplication is converted to just shift and add operation. Again all additions are done without carry propagation to avoid the carry propagation delay. Only in the last stage, carry look ahead adders are used to give final result. The present architecture is compared with any Traditional architecture reported for FFT processor. Because of the absence of multiplier and any carry propagate adder in the intermediate stages the power consumption as well as the hardware cost reduces. The critical delay also reduces significantly.