Test Bus Evaluation
Philip A. Dennis, S. Vining, Wayne W. Daniel, Jim Marisch · 1998
Abstract : The purpose of the Test Bus Evaluation report was to evaluate and document the applications and impact of standard test buses on overall system testability. Current and proposed test bus architectures were surveyed and identified as most appropriate for coordinating testability approaches between the chip and the system level. Eleven test bus architectures were investigated. A Data Gathering task was first undertaken to characterize the major attributes of the test buses. These attributes include the bus architecture, current status, functions supported, interface and number of pins, protocol, intended uses and speed. This data collection included a library search of existing literature that is documented in the Bibliography. Current and planned test bus extensions were explored and documented in the report. Test Bus control issues were investigated and documented to include hardware controller applications to device and module test buses, and test bus control software. Standard test bus control languages and vector formats are also addressed in this report.