A single chip multistandard video codec
S.C. Bose, Stephen C. Purcell, Tai-Yi Chiang · 2002
A programmable chip that implements multiple standards is described. Compliant with ISO MPEG (Moving Pictures Experts Group), it encodes or decodes SIF images at 30 frames/sec. It implements a P /spl times/ 64 full-duplex CIF codec at 15 frames/sec or QCIF at 30 frames/sec. It contains a glueless 80 Mbyte/sec DRAM (dynamic random-access memory) controller, a 240 MIPS (million instructions per second) SIMD (single instruction, multiple data) processor, and a 2000 MOPS (million operations per second) motion estimator. CCIR 601 video is input with high-quality conversion to SIF format, and a video display controller interpolates to 601 interlaced output.