A dual basis systolic divider for GF (2/sup m/)
S.T.J. Fenn, DAVID J. TAYLOR, Mohammed Benaissa · 2002
A bit-serial systolic divider for GF(2/sup m/) is presented. By virtue of being systolic this divider is modular, nearest neighbour connected and the longest delay path is independent of m and consequently it is well suited to VLSI implementation. Furthermore it is shown that this divider displays a number of advantages over a similar systolic divider, the foremost of which is that it operates over the dual basis. Circuits using this divider can therefore utilise other hardware efficient dual basis operators such as the Berlekamp multiplier.>