A fully Synchronous Circuit design for embedded DRAM
Akira Yamazaki, Naoto Okumura, Katsumi DOSAKA, Masaki Kumanoya · 2008
A fully synchronous circuit for embedded DRAMs is presented. It realizes accurate DRAM timing control, and easy timing adjustment. Using the circuit, software switching of the control timing is realized without difficulty. Providing handshake signals to on-chip memory-controller simplifies the memory-controller circuit in a CPU embedded DRAM. 1.