SVP: scan-line video processor-general purpose video processor
Hidetoshi Onuma, Y. Yaguchi, H. Miyaguchi, Tetsuya Akiyama, K. Kajiyama, K. Adachi, Akira Kikuchi, T. Kojima, Tetsu Narumi · 2002
The SVP achieved a fast processing rate exceeding standard DSPs by integrating 1024 PEs (Processing Elements). 50 MHz operation in each PE in the SIMD (Single Instruction Multiple Data) scheme is realized on two stage pipelines in the IG (Instruction Generator) and five stage pipelines in the PE CORE. With the realization of a 20 ns DRAM cycle in each PE and the system clock generated through a PLL, SVP enables full-spec-EDTV2 (the second generation Enhanced Definition Television in Japan).