A Parallel Implementation Of The Reverse Converter For The Moduli Set {2N, 2N–1, 2N–1–1}
Mehdi Hosseinzadeh, Amir Sabbagh Molahosseini, Keivan Navi · 2009
In this paper, a new reverse converter for the moduli set {2n, 2n–1, 2n–1–1} is presented. We improved a previously introduced conversion algorithm for deriving an efficient hardware design for reverse converter. Hardware architecture of the proposed converter is based on carry-save adders and regular binary adders, without the requirement for modular adders. The presented design is faster than the latest introduced reverse converter for moduli set {2n, 2n–1, 2n–1–1}. Also, it has better performance than the reverse converters for the recently introduced moduli set {2n+1–1, 2n, 2n–1}