An FFT systolic processor and its applications
T. Willey, T.S. Durrani, Roy Albert Chapman · 2005
Systolic architectures for signal processing are of great interest as they offer a considerable speed improvement over traditional Von-Nuemann computing architectures, and are particularly suitable for VLSI implementation due to ensuing simple and regular communication structures [1]. This paper presents an architecture for computing the Fast Fourier Transform (FFT) using a systolic processor which incorporates an elevator concept to circumvent the requirements for global communication inherent in conventional FFT implementations. The proposed algorithm is shown to be highly efficient in terms of both hardware and computation time. Architectures are further suggested for the real time computation of 2D functions such as the Wigner Distribution and the Complex Ambiguity function by using the systolic FFT processor coupled with an input characterising array.