A bit-level systolic 2D-IIR digital filter without feedback
Zhijian Hu, F.M.F. Gaston · 2002
This paper addresses the implementation aspect of a high performance bit-level systolic 2D IIR digital filter. A new data input scheme is used to solve the basic problem of latency in the feedback loop. The resulting design has increased parallelism and regularity. The simple modular structure leads to an efficient VLSI implementation. The filter has a throughput rate of one sample every clock cycle, which is twice that of previous published implementations.