Organization and statistical simulation of hierarchical multiprocessors
Jr. Andrew Wilkins Wilson · 1985
In order to provide high performance computing, the development of large scale multiprocessors is desirable. In the past, the performance of such processors has been substantially reduced by switching delays in the interconnection network and the inability to effectively use private caches due to cache problems. Meanwhile the design and development of such systems has been hindered by the large amount of time required to simulate large multiprocessors. This thesis proposes solutions to both problems, through a new family of multiprocessor architectures and new techniques for large system simulation. The multiprocessor architectures are based on the use of private, write-deferred caches with distributed multicache control which take advantage of the broadcasting ability inherent in shared bus interconnection networks. The thesis develops methods to extend the distributed control scheme to networks of multiple, hierarchical shared buses, thus allowing even larger systems. The extended control uses hierarchical caches as coherency guardians for groups of private caches. The hierarchical shared bus interconnection network allows direct access from all of the processors to all of the memory locations. The thesis analyses several specific architectures which incorporate the extended control and concludes that a cluster approach with distributed memory is best. The hierarchical simulation methodology developed in this thesis significantly reduces the amount of time required to simulate large multiprocessor architectures. The architectures are divided into a hierarchy of subsystems, with each subsystem simulated in detailed. The simulated subsystem behavior is then used when simulating the next higher level subsystems. The thesis demonstrates that reductions in simulation time of two orders of magnitude are possible. The thesis proposes methods for statistically capturing the behavior of subsystems as part of the recursive simulation strategy. Comparisons with direct simulations are performed which show that the statistical methods maintain good fidelity. Thus the new simulation methodologies are shown to be both accurate and efficient. Using the hierarchical simulation methodology, the thesis demonstrates that the proposed architecture is capable of nearly linear speedup for systems composed of over 100 processors. It is found that the extended cache control system produces little overhead, and that hierarchical caches can further reduce global bus bandwidth requirements.