Massive parallel processing for matrix multiplication: a systolic approach
David John Evans, C. R. Wan · WIT Press eBooks · 2001
In this chapter, we have designed nineteen systolic arrays for matrix multiplication under the framework of the systolic synthesis method using regular iterative algorithm (RIA) representation. Then we define different systolic array performance measures in order to evaluate the systolic designs. The performance of the designed systolic arrays is analysed in detail and this allows the comparison among the different systolic designs.