An embedded DSP core for wireless communication
Shyh-Jye Jerry Jou, Hsiao Ping Lee, Yi-Ting Chen, Ming Hsuan Tan, Ya-Lan Tsao · 2003
This paper proposes an embedded DSP core for communication applications with targets of demodulation/synchronization operation. Besides providing a basic instruction set, similar to current day 16-bit DSP processors, it contains distinguish instructions, and special function blocks like dual MAC, sub-word multiplier, dedicated FIR filter and multi-levels slicer, which make this DSP processor more efficient for several communication tasks. Also, the entire architecture is parameterized such that it can be embedded in a variety of applications. In the design of the chip, we adapt gray coded addressing for lowering switching activity, pipeline register sharing for reducing pipeline register and the entire architecture is used to reduce power dissipation. The DSP chip is implemented by synthesizable Verilog code with TSMC 0.35 /spl mu/m SPQM cell library. The equivalent gate count of the core without memory is about 50 k. The chip area is 4.10 mm*4.10 mm (with on chip memory).