Single chip VLSI realization of a neural net for fast decision making functions
Frank Stüpmann, S. Rode, G. Geske · 2004
The newest results of a hardware realization of a neural net for fast decision making functions in real time are shown here. There is a digital micro core with any functions-proceeding of the learning and testing of the net, supervising of training process and computation of some calculations in pre- and post-processing. The decision-making function is a trainable integrated analog neural network structure. The circuit not only contains the reproduction path but also the learning on-chip. Learning patterns for the neural chip are provided in a memory unit. These patterns are automatically presented to the network. The process of weight change (i.e. learning) is fully integrated. The information processing speed from the input to the output of the chip is 2 /spl mu/s in the reproduction process. The number of neurons integrated in the whole chip is 100 in the input layer, 60 in the hidden layer and 10 in the output layer. The back propagation algorithm is implemented in an analog circuit.