W-CDMA hardware-related issues
T. Ishikawa, Hajime Suzuki, N. Minamida, R. Yamanaka, Michio T. OKAMOTO, Hideyuki Kabuo, H. Taki · 2002
Overviews W-CDMA hardware-related issues and shows requirements for key devices of the W-CDMA and a solution for DSP, We propose a DSP architecture suited for W-CDMA. The main features of this architecture are: 1) highly efficient Viterbi error correction operation, 2) ability to perform a multiply-accumulate operation and store the result to data memory in a single cycle when used in conjunction with a repeat instruction, 3) support for the double precision (40 bit) operations and data, 4) ability to perform a DMA to/from a fixed portion of internal memory without interrupting the processor. These features allow implementation of a W-CDMA voice channel less than 100 MIPS.