5.4 GOPS linear array architecture DSP for video-format conversion
Masuyoshi Kurokawa, A. Hashiguchi, Kazuyuki Nakamura, Hiroshi Okuda, K. Aoyama, T. Yamazaki, Mitsuharu Ohki, Mitsuo Soneda, K. Seno, Ichiro Kumata, Masatoshi Aikawa, H. Hanaki, Seiichiro Iwase · 2002
A programmable DSP with linear-array architecture for real-time video processing, including video format conversion, has 4320 SIMD processor elements, has a peak processing rate of 5.4 GOPS, and can be applied to HDTV signals with its 75 MHz peak I/O clock rate. Sufficient programmability is provided to execute video-format conversion, such as image-size conversion (ISC) and Y/C separation, and picture-quality improvement, such as noise reduction and image enhancement.