A 19ns memory
A. Suzuki, Shuhei Yamaguchi, Hideo Ito, Noriyuki Suzuki, T. Yabu · 1987
A CMOS memory for cache systems which includes 49K bits SRAM and about 3500 transistors for logic will be presented. The memory achieves access times of 19ns from address to hit and 9.5ns from tag to hit, using address transition detection.