High‐speed flow‐based classification on FPGA
Tristan Groléat, Sandrine Vaton, Matthieu Arzel · International Journal of Network Management · 2014
SUMMARY Analyzing the composition of Internet traffic has many applications nowadays, like tracking bandwidth‐consuming applications, QoS‐based traffic engineering and lawful interception of illegal traffic. Even though many flow‐based classification methods, such as support vector machines (SVM), have demonstrated their accuracy, few practical implementations of lightweight classifiers exist. We consider in this paper the design of a real‐time SVM traffic classifier at hundreds of Gb/s to allow online detection of categories of applications. We also implement a high‐speed flow reconstruction algorithm able to handle one million concurrent flows. The solution is based on the massive parallelism and low‐level network interface access of FPGA boards. We find maximum supported bit rates up to 408 Gb/s for classification and up to 20 GB/s for flow reconstruction for the most challenging trace. Results are confirmed using a commercial Combov2 board with a Virtex 5 FPGA. Copyright © 2014 John Wiley & Sons, Ltd.