A high-speed FFT processor for OFDM systems
Bong Soo Son, B.G. Jo, Myung Hoon Sunwoo, Yong Serk Kim · 2003
This paper proposes a high-speed FFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed architecture uses a single-memory for a small hardware size and uses a radix-4 algorithm for high speed. Its memory is partitioned into four banks for high-speed computation. It uses an in-place memory strategy that stores butterfly outputs in the same memory location used by butterfly inputs. The architecture has been modeled by VHDL and logic synthesis has been performed using the Samsung/sup /spl trade// 0.5/spl mu/m SOG cell library (KG80). The implemented FFT processor consists of 98,326 gates excluding RAM. The processor can operate at 42MHz and calculate a 256-point complex FFT in 6/spl mu/s.