An analog parallel array processor for real-time sensor signal processing
Peter R. Kinget, M. Steyaer · 2002
A fully-programmable analog signal processor and its operation in a sensor signal processing system is presented. The analog parallel array processor (APAP) chip is the core of the system. It contains a 20/spl times/20 matrix of computing cells, function-control circuits and interface circuits. The sensor provides the input signals for the APAP chip. The architecture ofthe 400 cells is based on a cellular neural network architecture. The cells have an internal-state node, an input node and an output. The output is the clipped version ofthe state. The cells send two current signals to their nearest neighbors and to itself: one proportional to the input and controlled by the feedforward weights or B-template; the second proportional to the output and controlled by the feedback weights or A-template. In every cell a constant bias source, controlled by the I-template, is also included. The templates are identical for all cells and are the instructions for the APAP. In this implementation the user can program the template weights over a continuous range of values from /spl plusmn/1/4 to /spl plusmn/4. All cells execute the instructions in parallel and in continuous time so that a parallel array processor is obtained with real-time signal processing capabilities. Several 2D global and local feature extraction operations such as edge detection, pixel peeling, hole-filling, connected component detection, and resistive grid filtering can be executed.