Architectures for adaptive weight calculation on ASIC and FPGA
Richard L. Walke, ROBERT WILLIAM SMITH, Gaye Lightbody · 2003
We compare two parallel array architectures for adaptive weight calculation based an QR-decomposition by Givens rotations. We present FPGA implementations of both architectures and compare them with an ASIC-based solution. The throughput of the FPGA implementations is of the order 5-20 GigaFLOPS, making FPGA a viable alternative to ASIC implementation in applications where power consumption and volume cost are not critical.