Balancing batteries, power, and performance: system issues in cpu speed-setting for mobile computing
Daniel P. Siewiorek, Thomas L. Martin · 1999
This thesis studies the problem of balancing power and performance in mobile computers, specifically, trading off power for performance by CPU speed-setting. The traditional approach to power-performance trade-offs assumes that batteries and memory bandwidth are ideal and focuses on lowering the energy per operation. This research, however, shows that non-ideal battery and performance behavior must be considered to properly balance power and performance, and that computations per battery life is a better metric for powerperformance trade-offs than energy per operation. The thesis begins with a description of non-ideal battery properties that can affect powerperformance trade-offs and then presents models for those properties. The models delineate regions where batteries can be treated ideally and where their non-ideal behavior must be considered. Furthermore, the models show that peak power rather than average power determines the available battery capacity. Thus, the first major result is that decreasing a mobile computer’s active power will increase the battery life more than decreasing its idle power, even if both reduce the average power by the same amount. The thesis then shows that the memory system also has an impact on CPU speed-setting. Because of limits in memory bandwidth, code performance will not scale with CPU speed when there are a considerable number of accesses to main memory. The second major result is to show that, because of non-ideal memory performance and non-ideal battery capacity, the results of some experiments are nearly a factor of four less for a real system than what would be expected using the ideal assumptions. For those experiments, the computations per discharge is expected to increase by 230%, but instead the measured results show a 37% decrease. Consequently, a system-level approach to CPU speed-setting should account for the nonidealities of both the memory and the battery. The final major result is an outline of a realistic method for CPU speed-setting, one that accounts for non-ideal memory and battery behavior by using performance-monitoring registers and battery “gas gauge” integrated circuits.