A leakage-tolerant low-leakage register file with conditional sleep transistor
Amit Agarwal, Kaushik Roy, Ram Kumar Krishnamurthy · 2004
This paper describes a 256/spl times/64b 3-read, 3-write ported leakage tolerant low leakage register file. The local bitline shares a sleep transistor for aggressive bitline leakage reduction/tolerance to enable high fanin bitlines and uses low V/sub th/ transistors. The sleep transistor is turned on while accessing the local bitline and conditionally turned off, if the dynamic node should remain high. Simulation results shows that proposed technique achieves 9% improvement in performance with 14/spl times/ reduction in local bitline leakage (97/spl times/ reduction as compared to any previously proposed low V/sub th/, leakage tolerant register file) enabling 70% reduction in keeper size, while keeping the same noise robustness as optimized high performance conventional high V/sub th/ implementation.