Topological maps for VLSI placement
R. Sadananda, Aadit Shrestha · 2005
This paper describes a method of using topological maps in the placement of VLSI cells. A number of algorithms for placement has been reported in view of its importance in the overall VLSI design. The problem in NP-hard. The self-organizing methods shown here can serve as important first draft of the design. The inherent limitation of the serial nature of this method can be overcome by appropriate partition of the input space and also in conjunction with other known methods of VLSI design.