A dynamically reconfigurable interconnection chip
Chin-Yuan Chin, Wen-Tai Lin, Juh-Ping Hwang, Sow Chu, G.A. Forman, R. Dunki-Jacobs, S. Karr, J.A. Mallick, H. T. Kung, Alan Sussman, Fang-Hsuan Hsu, Teiji Nishizawa · 1987
This paper will describe a 70K transistor chip fabricated in a 1.25μm CMOS technology, with a 6.2×7.6mm die size, and featuring data synchronization, pipeline latency compensation and other computational elements.