A radix-2/3/22/23 MDC architecture for variable-length FFT processors
Hsin-Fu Luo, Ming‐Der Shieh, Kun-Hsien Lee · 2015
A radix-2/3/22/23multi-path delay commutator (MDC) architecture for pipelined shared-memory fast Fourier transform (FFT) processors is proposed. By using an effective memory addressing scheme, the original processing and control characteristics of the 2m-point FFT processor are retained when processing 3·2m-point FFT, where m is an integer. The proposed variable-length FFT processor can thus be implemented more efficiently.