A write-back cache memory using bit-line steal technique
A. Miyoshi, H. Okuyama, S. Ozaki, T. Tsuki, Keisuke Kaneko, S. Ogura, Y. Nishimichi · 2002
The authors describe a low-cost high-speed cache memory including a Write Back Buffer (WBB). Since the WBB is located in a cache memory, and connected with memory cells through bit-lines, memory data is copied to the WBB in 1-clock cycle. This cache memory is in a 32 bit microcontroller developed by the authors.