A time-division broadband switching network using a frame synchronization technique
S.-i. Hayano, T. Takeuchi, Kunio Nagashima · 2003
A time-division broadband switching network for signal channels of up to 150 Mb/s is studied. Two problems commonly arise in such networks. One is the inability to expand switching capacity because of the low multiplexity of time switches. The other is the signal delay in the wiring. To avoid these problems, the authors propose a serial-highway memory matrix switching network using a frame synchronization technique which automatically compensates for transmission delays of highway signals. This architecture is suitable for high-speed LSIs, such as GaAs LSIs, because an elementary memory switch needs only a small number of logic gates. Moreover, this switch configuration offers space switch functions as well as time switch functions. Thus, the switching network can be expanded within building-block style using only memory matrix LSIs. The authors show that the proposed method makes it possible to design a switching network with a capacity of more than 4000 lines without needing to worry about transmission delays.>