A 32b 64-word 9-read-port/7-write-port pseudo dual-bank register file using copied memory cells for a multi-threaded processor
M. Sumita, Y. Ikeda · 2005
A method for copying memory cells to reduce the size of the register file for a multi-threaded processor is proposed. The number of transistors in the memory cell is reduced to 70% and the total bit and word lines is reduced to 63%. The register file is implemented in a 100nm CMOS process. The size of the register file is reduced to 62% of a conventional register file. The power consumption is reduced by 50%.