Fast transform processor implementation
Earl E. Swartzlander, G. Hallnor · 2005
This paper describes recent progress in implementation of a 40 MHz (complex) data rate frequency domain adaptive digital filter. The filter uses multiple time overlapped channels each consisting of an FFT, a frequency domain multiplier, and an inverse FFT. The 4096 point FFT and inverse FFT processors realize the McClellan and Purdy radix 4 pipeline FFT algorithm with 22 bit floating point arithmetic. The arithmetic is performed with single chip floating point adders and multipliers. The interstage reordering is performed with a delay commutator implemented with semi-custom VLSI. By using state of the art arithmetic components and judicious semi-custom circuit development, an FFT processor has been implemented that computes a 4096 point (complex) transform in 102 microseconds.