Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach
Chung-Hsin Liu, Chiou‐Yng Lee, Pramod Kumar Meher · IEEE Transactions on Circuits and Systems I Regular Papers · 2015
It is well-known that the (a,b)-way Karatsuba algorithm (KA) with a ≠ b is used for efficient digit-serial multiplication with subquadratic space complexity architecture. In this paper, based on (a,b)-way KA decomposition, we have derived a novel k-way block recombination KA (BRKA) decomposition for digit-serial multiplication. The proposed k-way BRKA is formed by a power of 2 polynomial decomposition. By theoretical analysis, it is shown that k-way BRKA can provide the necessary tradeoff between space and time complexity. Using (4,2)-way KA to construct the proposed k-way BRKA architecture in GF(2409), it is shown that the proposed 2-way BRKA approach requires less area, and the proposed 8-way BRKA approach requires less computation time and less area-time product compared to compared the existing (a,b)-way KA decomposition.