A Fair Scheduling Algorithm for Input-Queued Switches
Hua-An Zhao, Qingsheng Hu · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2009
To increase both the capacity and the processing speed for input-queued (IQ) switches, we proposed a fair scalable scheduling architecture (FSSA) where several chips of cascaded sub-scheduler compose a large-scale high performance network scheduler. In this paper, we present an improved scheduling algorithm named DIFSSA where a distributed iteration scheme is employed based on FSSA. The simulation and measurement results show that DIFSSA achieves better performance on average delay and throughput under heavy loads compared to existing algorithms and its scheduler performance and the processing time are also better than the other. Moreover, it has been implemented by 4 Xilinx FPGAs as 64×64 switch whose data rates can be up to 800Mbps and the tradeoff between performance and hardware complexity has been solved peacefully.