Tightly coupled multiprocessor system speeds memory-access times
Steven Frank · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1984
A tightly coupled architecture of multiple processors automates the functions of expansion, system tuning, load balancing and data-base distribution-a major part of designing and implementing online systems. To reduce memory-access times significantly, the n+1 multiprocessor system for fault-tolerant transaction processing also combines individual cache memories for each processor with a data-sharing scheme. Thus it overcomes the problems which have prevented other designs from realising the increased performance a tightly coupled multiprocessor architecture should provide. The principal problem resulted from the use of a shared memory, because the individual processors contend for that memory and therefore waste much valuable processing time. The n+1 architecture, with individual cache memories and a 'bus-ownership protocol,' has overcome this impediment and offers linear increases of performance, with up to 28 processors sharing a common fault-tolerant memory system. The key to the synapse expansion architecture is a new look at bus arbitration and caching in tightly coupled systems.