Environment for FPGA-based Fault Emulation
Peeter Ellervee, Jaan Raik, Kalle Tammemäe, Raimund Ubar · 2006
Abstract. This paper describes an environment to accelerate fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated with fault simulation of digital circuits are explained. The proposed approach allows simulation speed-up of 40 to 500 times as compared to the state-of-the-art in software-based fault simulation. Based on the experiments, it can be concluded that it is beneficial to use emulation for circuits that require large numbers of test vectors while using simple but flexible algorithmic test vector generating circuits, e.g. built-in self-test. Key words: fault simulation, acceleration, emulation, field-programmable logic. 1.