High-Level Test Synthesis with Hierarchical Test Generation
Gert Jervan, Petru Eles, Zebo Peng, Jaan Raik, Raimund Ubar · 1999
A novel full design and test generation system with combined High-Level Synthesis (HLS) and automated Hierarchical Test Pattern Generation (HTPG) was developed and experimented. The high-level synthesis is based on representation model called Extended Timed Petri Net (ETPN). In the test generator both register-transfer (RT) and gate-level descriptions are used, and Decision diagrams (DD) are exploited as a uniform model for describing systems at both levels. In addition to the synthesis and test generator tools, interfaces to behavioral and RT-level VHDL and EDIF netlist formats have been implemented. In the paper, an overview of the implementation is given and experimental data showing the viability of the approach and the efficiency of respective tools are provided.