DESIGN OF THE SPECIAL FAST RECONFIGURABLE CHIP USING COMMON FPGA
Lukáš Sekanina · 2001
Some applications require chips with fast partial reconfiguration. These requirements are traditionally satisfied by a special chip design, but it is usually a very expensive solution. This paper describes a new approach. Special fast partially reconfigurable chip is implemented with a common FPGA. The format of the configuration bit stream is suggested and optimized according to the given task. Result chip offers many good properties, but some problems with scalability can appear.