ADARC: A New Multi-Instruction Issue Approach.
Frank Henritzi, Andreas Bleck, R. Moore, Bernd Klauer, Klaus Waldschmidt · 1996
The Associative Dataflow Architecture (ADARC) combines features usually associated with either VLIW or with dataflow architectures to achieve an efficient exploitation of the instructionlevel parallelism of numerical algorithms on a modular, scalable, parallel hardware with distributed memory. While the ADARC architecture does not favorize any final implementation considering the complexity of the used functional units, this paper focuses on a realization which is similar to VLIW-based processors. ADARC extends the synchronous issuing of operations in VLIWs to an asynchronous mechanism allowing arbitrary execution times and different issuing times of the simple instructions out of one VLIW. This new sequencing method is efficiently supported by an intelligent interconnection network performing transport triggering mechanisms using associatively controlled switches as routing elements. Keywords: computer architecture, multi-instruction issue, scalable interconnection networks, dataflow...