Analysis and Implementation of Built-In Self-Test for Block Random Access Memories in Virtex-5 Field Programmable Gate Arrays
Justin L. Dailey · 2011
In order to ensure the proper operation of the embedded Block Random Access Memories (BRAMs) in Xilinx Virtex-5 Field-Programmable Gate Arrays (FPGAs) a dependable and resource efficient test is needed so that the integrity of the memory can be guaranteed in a timely manner. The approach that is described in this thesis is based on a Built-In Self-Test (BIST) approach initially proposed by Garimella in [1] for Xilinx Virtex-1 and Virtex-2 FPGAs. It was later expanded upon by Milton in [2] for Xilinx Virtex-4 FPGAs. The work was continued by Garrison as detailed in [3] for Virtex-4 in order to improve BIST generation and execution time. Garrison also proposed a design for BRAM BIST for Virtex-5 FPGAs in [3]. Garrison‟s proposal for Virtex-5 FPGAs is expanded upon and implemented in this thesis. The testing approach for these BRAMs is described along with testing configurations and details. The BIST configurations are implemented using five unique Test Pattern Generators (TPGs) running testing algorithms on a combination of 19 separate RAM configurations in order to fully test the memories. All of the BIST configurations have been generated using two C programs developed as part of this thesis which are capable of generating configurations for any Virtex-5 device. These configurations were downloaded to various Virtex-5 FPGAs and tested